The present invention relates to a method for providing at least one inductance associated with a chip attached to a support, in which said inductances are provided by means of at least a first bondwire having first and second ends, and in which said first end of said first bondwire is bonded to a first pad on said chip by means of an automated process using the chip as a reference for placing the first end of the first bondwire on the first pad when bonding it thereto.
Integrated circuit packages usually consist of at least one semiconductor chip, which is often referred to as a die, and electrical conductors providing the communication to the exterior. The chip is mounted on a support, e.g., an interposer or a lead-frame, by means of gluing or a similar fastening method. To finish the package, the assembly of chip, support and electrical conductors, is moulded in by means of an appropriate plastic material, thus sealing the assembly and leaving only terminals in the form of pads or pins protruding to the exterior. Alternatively the sealing can be made by fastening a cover made of plastic, a ceramic material, or some other appropriate material, to the support.
The electrical conductors providing the communication to the exterior, are usually made from gold or aluminum threads, which are at one end connected to terminal pads on the chip, and at the other end connected to metal plated pads on the support, the pads themselves being connected to the exterior in some manner. These threads are commonly referred to as bondwires.
All conductors, and thus also the bondwires, exhibit an inductance. However, since the bondwires are relatively short, their inductance is so small that it is not of importance at low frequencies. For this reason the inductance of the bondwires has largely been ignored.
In connection with chips working at radio frequencies (RF), or otherwise designed for RF applications, the inductances cannot be ignored. This gives the circuit designer the choice of either minimizing the inductive effect of the bondwires, or deliberately target the inductance of the bondwires for the use as a circuit component.
The use of bondwires to provide specific inductances, is suggested in the article xe2x80x9cA I 0.8-GHz CMOS Low-Phase-Noise Voltage-Controlled Oscillator with Prescalerxe2x80x9d, Craninckx, J. and Steyaert, M. S. J., IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 30, No. 12, Dec. 1995, pages 1474 to 1482. The article states that to be able to predict the inductance value as correctly as possibly the length of the bond wires must be controlled accurately, because the length of the bondwire is the main factor determining its inductance. As a solution the article suggests the use of on-chip bond wires.
U.S. Pat. No. 886,393 also deals with the use of bondwires for providing an inductance. In this patent the bondwires are looped around between pads on the chip or the support to form a coil. The problem of inductance precision is not dealt with in the patent.
The use of on-chip bondwires provides quite predictable results because the pads are situated on the chip and their relative position thus fixed with the high accuracy of the chip manufacturing process. Since the distance between the pads is well known, the length of bondwire, and thus the inductance, is predictable.
The on-chip approach though, has one major drawback, namely how to bond the second end of the bondwire to the chip. Ends of bondwires are normally connected to pads using one of two methods, ball-bonding and wedge-bonding. Ball-bonding is normally used to bond the first end of the bondwire to a pad on the chip, wedge-bonding is normally used to bond the second end of the bondwire to a pad on the support. A wedge-bond places considerable stress on the pad, and is normally not considered suitable for use on the chip. Thus, if a wedge-bond is used to connect the second end of the bondwire to the chip, special precautions must be taken not to damage the chip. If a ball-bond is used the procedure is quite complicated, the wire must be severed and end heated to form a ball, then the end must be placed on the pad and bonded. The procedure of making a second ball-bond is so complicated that it rarely, if ever, is used for mass production. Either way this makes the approach expensive.
Another drawback of placing all the pads are on the chip, is that they take up a large portion of the chip area, which is then wasted.
Placing all bondwire inductors on another surface with more rugged pads 20 leaves the problem of connecting the inductor.
In a hybrid solution where some of the pads are placed on the chip and others on another surface inside of the IC package, e.g. on the support, the value of the inductors becomes less predictable.
This is due to the fact that the positioning of the chip on the support in the IC package, using standard production methods, has much wider tolerances than the positioning of a pad on the chip. This tolerance is compensated for by the bondwire.
The way this compensation is effected is that when the first end of the bondwire is placed on the pad on the chip the positioning is done relative to the chip, whereas when the second end of the bondwire is placed on the pad on the support this is done relative to the support.
In this way the positioning of both ends of the bondwire is correct, with regard to the respective pad to which it is attached, even if the position of the chip on the support deviates from one IC package to another.
The result being that the tolerances on the positioning of the chip on the support in the IC package is reflected in the length of the bondwires and thus in their inductance, the inductance of a bondwire being roughly 1 Nh/mm.
According to a first aspect of the invention there is established a method for providing at least one inductance associated with a chip attached to a support, in which said inductances are provided by means of at least a first bondwire having first and second ends, and in which said first end of said first bondwire is bonded to a first pad on said chip by means of an automated process using the chip as a reference for placing the first end of the first bondwire on the first pad when bonding it thereto, characterized in that said second end of said first bondwire is bonded to a second pad on said support by means bf the automated process using the chip as a reference for placing the second end of the first bondwire on the second pad when bonding it thereto. The object of the present invention is to overcome the above problems in providing well defined inductances associated with a chip.
In other words, according to the invention the problems outlined above are solved by placing the first end of the bondwire on the chip and the second end of the bondwire on the support and positioning both ends of the bonding wire relative to the chip. In order to use the chip as a reference of both ends of the bonding wire, it is however necessary to enlarge the connection pads on the support accordingly so as to compensate for the tolerances.
According to a second aspect of the invention there is provided an integrated circuit package including a chip, a support to which the chip is attached, and at least one bondwire extending from a first pad on the chip to a second pad on the support and electrically connecting the first and the second pads, characterized in that the smallest dimension on the second pad is at least six times the diameter of the bondwire.
Thus, with the invention, the length of the bondwire remains the same from one IC package to another, but in the different IC packages the second end of the bondwire will be positioned in different places on the respective pad on the support to which it is attached. The only compromise necessary is the use of enlarged connection pads, but enlarging these pads will not pose any problems, since usually the IC package, and in particular the supporting surface for the enlarged connection pads is much larger than the chip itself, thus providing ample room for the bondwires.
Further the support is much less expensive, compared to the chip, because the support basically is comparable with a printed circuit board, whereas the chip itself is a high precision semiconductor part.
The invention will now be explained in greater detail by means of a non-limiting exemplary embodiment, and the drawings.